risc-v¶
Backend for the risc-v platform. See also: https://riscv.org/
Testing¶
To test the riscv platform, the picorv32 project is used.
Module¶
See also: http://riscv.org
Contributed by Michael.
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class
ppci.arch.riscv.
RiscvArch
(options=None)¶ -
between_blocks
(frame)¶ Generate any instructions here if needed between two blocks
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determine_arg_locations
(arg_types)¶ Given a set of argument types, determine location for argument ABI: pass args in R12-R17 return values in R10
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determine_rv_location
(ret_type)¶ Determine the location of a return value of a function given the type of return value
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gen_call
(frame, label, args, rv)¶ Implement actual call and save / restore live registers
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gen_epilogue
(frame)¶ Return epilogue sequence for a frame. Adjust frame pointer and add constant pool
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gen_function_enter
(args)¶ Generate code to extract arguments from the proper locations
The default implementation tries to use registers and move instructions.
Parameters: args – an iterable of virtual registers in which the arguments must be placed.
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gen_prologue
(frame)¶ Returns prologue instruction sequence
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get_runtime
()¶ Implement compiler runtime functions
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litpool
(frame)¶ Generate instruction for the current literals
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move
(dst, src)¶ Generate a move from src to dst
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